Why 0.01nm semiconductors are possible right now.JPG

In the current EUV mask process, the device size on the mask is reduced,
and semiconductors with high resolution are patterned by reflecting light with a short wavelength.
This is because for even smaller masks to be properly developed, the wavelength must be even shorter.
Instead of increasing the integration density of the mask or reducing the wavelength, a method to reduce the light was found.
The mask is kept at a size for developing 2nm, the reflected light density is lowered by passing it through a lens filter,
and then it is developed using a lens that increases the reduction magnification.
As a result, 2nm is reduced from 50x to 50,000x, allowing for the development of 0.01nm to 0.00001nm sizes.
However, to make the ingot particles existing between devices possess semiconductor characteristics, the density of the ingot must be increased.
Therefore, a new process is added during ingot production:
Carbon is mixed into the ingot and heated to a liquid state, carbon ions are added and mixed,
it is compressed as an insulator, and then pulled by the electric field of an ultra-powerful external magnet.
The material inside the ingot is pulled by the electric field to create an ultra-high-density ingot, which is then cooled.
Then, the ingot is cut in half; one half is used and the other half is discarded.
By lowering the light density produced in 2nm EUV and increasing the reduction magnification,
0.01nm semiconductors were patterned onto the wafer. It takes 100 repetitions to pattern a 3CM X 3CM area.
Then, the yield of the 3CM X 3CM semiconductor must be verified.
Since the size is 0.01nm, it has an integration density 100 times higher than 1nm,
and by patterning 100 times, 100 independent chipsets are drawn.
If all 100 work, they can be divided into 100 units for independent use.
However, if 30 out of 100 work and 70 do not,
even the 30 that work do not function as entire chipsets, but only as fragments covering 1/3 of the area.
Like fragments of paint spreading when ink is sprayed, only semiconductor devices covering about 1/3 of the area function.
It is not that a single intact chipset works; rather, 2/3 of a single chipset does not even show an electrical response.
Therefore, the mask device design for the wafer must be different;
instead of requiring a single chipset to be perfectly developed to function,
it is designed so that it can function even if only a part is developed.
As a supplementary concept, it is developed using a mask that patterns 0.01nm to 0.00001nm devices.
A main chipset is made at 2nm that must be 100% perfectly developed to function,
and then 90 semiconductors of 0.01nm to 0.00001nm are inserted behind it.
Even if 90% of the 90 units do not work, even if only 10% work,
the energy efficiency and semiconductor performance become incredibly high,
but a 2nm main chipset is absolutely necessary to operate the 0.01nm to 0.00001nm semiconductors.
From this, a new type of semiconductor is born, where 2nm is the main component and 0.1nm to 0.0001nm are the auxiliary components.
In the future, one 2nm unit could be installed, and performance could be increased by mounting multiple 0.01nm and 0.00001nm semiconductor chipsets as auxiliaries.